document number: 91083 www.vishay.com s11-1051-rev. c, 30-may-11 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet irf9620s, sihf9620s vishay siliconix features ? halogen-free according to iec 61249-2-21 definition ? surface mount ? available in tape and reel ? dynamic dv/dt rating ? p-channel ?fast switching ? ease of paralleling ? simple drive requirements ? compliant to rohs directive 2002/95/ec description the power mosfets technology is the key to vishays advanced line of power mosfet transistors. the efficient geometry and unique processing of the power mosfets design achieve very low on-s tate resistance combined with high transconductance and extreme device ruggedness. the d 2 pak (to-263) is a surface mount power package capable of accommodating di e sizes up to hex-4. it provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. the d 2 pak (to-263) is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 w in a typical surface mount application. note a. see device orientation. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 5). b. not applicable c. i sd ? - 3.5 a, di/dt ? 95 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. e. when mounted on 1 square pcb (fr-4 or g-10 material). product summary v ds (v) - 200 r ds(on) ( ? )v gs = - 10 v 1.5 q g (max.) (nc) 22 q gs (nc) 12 q gd (nc) 10 configuration single s g d p-channel mosfet d 2 pak (to-263) g d s ordering information package d 2 pak (to-263) d 2 pak (to-263) lead (pb)-free and halogen- free sihf9620s-ge3 sihf9620strl-ge3 a lead (pb)-free IRF9620SPBF irf9620strlpbf a sihf9620s-e3 sihf9620stl-e3 a absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 200 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 c i d - 3.5 a t c = 100 c - 2.0 pulsed drain current a i dm - 14 linear derating factor 0.32 w/c linear derating factor (pcb mount) e 0.025 inductive current, clamp i lm - 14 a maximum power dissipation t c = 25 c p d 40 w maximum power dissipation (pcb mount) e t a = 25 c 3.0 peak diode recovery dv/dt c dv/dt - 5.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91083 2 s11-1051-rev. c, 30-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irf9620s, sihf9620s vishay siliconix note a. when mounted on 1" square pcb (fr-4 or g-10 material). notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 5). b. pulse width ? 300 s; duty cycle ? 2 %. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja --62 c/w maximum junction-to-ambient (pcb mount) a r thja --40 maximum junction-to-case (drain) r thjc --3.1 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0, i d = - 250 a - 200 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = - 1 ma - - 0.22 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = - 200 v, v gs = 0 v - - - 100 a v ds = - 160 v, v gs = 0 v, t j = 125 c - - - 500 drain-source on-state resistance r ds(on) v gs = - 10 v i d = - 1.5 a b --1.5 ? forward transconductance g fs v ds = - 50 v, i d = - 1.5 a 1.0 - - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 10 - 350 - pf output capacitance c oss - 100 - reverse transfer capacitance c rss -30- total gate charge q g v gs = - 10 v i d = - 4.0 a, v ds = - 160 v, see fig. 11 and 18 b --22 nc gate-source charge q gs --12 gate-drain charge q gd --10 turn-on delay time t d(on) v dd = - 100 v, i d = - 1.5 a, r g = 50 ? , r d = 67 ? , see fig. 17 b -15- ns rise time t r -25- turn-off delay time t d(off) -20- fall time t f -15- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 3.5 a pulsed diode forward current a i sm --- 14 body diode voltage v sd t j = 25 c, i s = - 3.5 a, v gs = 0 v b --- 7.0v body diode reverse recovery time t rr t j = 25 c, i f = - 3.5 a, di/dt = 100 a/s b - 300 450 ns body diode reverse recovery charge q rr -1.92.9nc forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
document number: 91083 www.vishay.com s11-1051-rev. c, 30-may-11 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irf9620s, sihf9620s vishay siliconix typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical transfer characteristics fig. 3 - typical saturation characteristics fig. 4 - maximum safe operating area fig. 5 - maximum effective transient thermal impedance, junction-to-case vs. pulse duration 91083_01 80 s pulse test v ds , drain-to-source voltage (v) i d , drain current (a) - 10 - 5 v gs = - 10, - 9, - 8, - 7 v - 4 v - 6 v - 5 v - 4 0 - 1 - 2 - 3 0 - 50 - 40 - 30 - 20 91083_02 v gs , gate-to-source voltage (v) i d , drain current (a) - 2 - 5 - 4 0 - 1 - 2 - 3 0 - 10 - 8 - 6 - 4 80 s pulse test v ds > i d(on) x r ds(on) max. t j = - 55 c t j = 25 c t j = 125 c 91083_03 v ds , drain-to-source voltage (v) i d , drain current (a) - 1 - 5 - 4 0 - 1 - 2 - 3 0 - 5 - 4 - 3 - 2 80 s pulse test v gs = - 10, - 9, - 8, - 7 v - 4 v - 6 v - 5 v 100 s 1 ms 10 ms operation in this area limited by r ds(on) negative v ds , drain-to-source voltage (v) negative i d , drain current (a) t c = 25 c t j = 150 c single pulse 10 2 2 5 0.1 1 2 5 10 2 5 25 110 25 10 2 10 3 25 91083_04 2.0 1.0 0.1 10 -5 10 -4 10 -3 10 -2 0.1 1.0 10 p dm t 1 t 2 t 1 , square wave pulse duration (s) z thjc (t)/r thjc , normalized effective transient notes: 1. duty factor, d = t 1 /t 2 2. per unit base = r thjc = 3.12 c/w 3. t jm - t c = p dm z thjc (t) single pulse (transient thermal impedence) 0.2 0.05 0.02 0.01 91083_05 0.1 d = 0.5 0.5 0.2 0.05 0.02 0.01 25 25 25 25 25 25 thermal impedence (per unit)
www.vishay.com document number: 91083 4 s11-1051-rev. c, 30-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irf9620s, sihf9620s vishay siliconix fig. 6 - typical transconductance vs. drain current fig. 7 - typical source-drain diode forward voltage fig. 8 - breakdown voltage vs. temperature fig. 9 - normalized on-resistance vs. temperature fig. 10 - typical capacitance vs. drain-to-source voltage fig. 11 - typical gate charge vs. gate-to-source voltage 4.0 g fs ,transconductance (s) i d , drain current (a) - 1 - 2 - 3 - 4 - 5 0 t j = 25 c t j = - 55 c 91083_06 t j = 125 c 80 s pulse test v ds > i d(on) x r ds(on) max. 3.2 2.4 1.6 0.8 0.0 t j = 25 c t j = 150 c - 20 v sd , source-to-drain voltage (v) i dr , reverse drain current (a) - 2.0 - 6.8 - 5.6 - 4.4 - 3.2 91083_07 - 0.1 - 0.2 - 1.0 - 2 - 5 - 10 - 8.0 - 0.5 91083_08 t j , junction temperature (c) bv dss , drain-to-source breakdown 1.25 voltage (normalized) 1.15 0.75 0.85 0.95 1.05 - 40 160 120 80 40 0 91083_09 t j , junction temperature (c) r ds(on) , drain-to-source on resistance 2.5 (normalized) 2.0 0.0 0.5 1.0 1.5 - 40 160 120 80 40 0 i d = - 1.0 a v gs = - 10 v 91083_10 v ds , drain-to-source voltage (v) c, capacitance (pf) 500 0 100 200 300 400 0 - 50 - 40 - 30 - 20 - 10 c iss c rss c oss v gs = 0 v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gs , c gd c gs + c gd c gs + c gd q g , total gate charge (nc) negative v gs , gate-to-source voltage (v) 20 16 12 8 0 4 04 16 12 8 v ds = - 40 v v ds = - 60 v for test circuit see figure 18 v ds = - 100 v 91083_11 i d = - 3.5 a 20
document number: 91083 www.vishay.com s11-1051-rev. c, 30-may-11 5 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irf9620s, sihf9620s vishay siliconix fig. 12 - typical on-res istance vs. drain current fig. 13 - maximum drain current vs. case temperature fig. 14 - power vs. temperature derating curve fig. 15 - clamped inductive test circuit fig. 16 - clamped inductive waveforms fig. 17a - switching time test circuit fig. 17b - switching time waveforms 91083_12 i d , drain current (a) r ds(on) , drain-to-source r ds(on) measured with current pulse of 2.0 s duration. initial t j = 25 c. (heating effect of 2.0 s pulse is minimal.) 0 1 2 3 4 5 0 - 20 - 16 - 8 - 4 - 12 on resistance ( ) v gs = - 10 v v gs = - 20 v 150 negative i d , drain current (a) t c , case temperature (c) 0.0 1.5 2.0 2.5 3.0 3.5 25 91083_13 125 100 75 50 1.0 0.5 t c , case temperature (c) p d , power dissipation (w) 40 35 20 0 5 0 20 100 80 60 40 91083_14 140 120 30 25 15 10 0.05 d.u.t. l v ds + - v dd v gs = - 10 v var y t p to obtain required i l t p v dd = 0.5 v ds e c = 0.75 v ds e c i l v dd v ds t p e c i l pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd v gs 10 % 90 % v ds t d(on) t r t d(off) t f
www.vishay.com document number: 91083 6 s11-1051-rev. c, 30-may-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irf9620s, sihf9620s vishay siliconix fig. 18a - basic gate charge waveform fig. 18b - gate charge test circuit fig. 19 - for p-channel vishay siliconix maintains worldwide manufa cturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91083 . q gs q gd q g v g charge - 10 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - p.w. period di/dt diode recovery dv/dt body diode forward drop body diode forward current driver gate drive inductor current d = p.w. period + - - - - + + + peak dio d e recovery d v/ d t test circuit ? dv/dt controlled by r g ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low stray inductance ? g round plane ? low leakage inductance current tran s former r g ? compliment n-channel of d.u.t. for driver v dd ? i s d controlled by duty factor d note note a. v gs = - 5 v for logic level and - 3 v drive device s v gs = - 10 v a d.u.t. l s d waveform d.u.t. v d s waveform v dd re-applied voltage ripple 5 % i s d rever s e recovery current
document number: 91364 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-263ab (high voltage) notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimensions are shown in millimeters (inches). 3. dimension d and e do not include mold flash. mold flash shal l not exceed 0.127 mm (0.005") per side. these dimensions are me asured at the outmost extremes of the plastic body at datum a. 4. thermal pad contour optional within dimension e, l1, d1 and e1. 5. dimension b1 and c1 apply to base metal only. 6. datum a and b to be determined at datum plane h. 7. outline conforms to jedec outline to to-263ab. 5 4 1 3 l1 l2 d b b e h b a detail a a a c c2 a 2 x e 2 x b 2 2 x b 0.010 a b mm 0.004 b m base metal plating b 1, b 3 ( b , b 2) c1 (c) section b - b and c - c scale: none lead tip 4 34 (dat u m a) 2 c c b b 5 5 v ie w a - a e1 d1 e 4 4 b h seating plane ga u ge plane 0 to 8 detail ?a? rotated 90 cw scale 8 :1 l3 a1 l4 l millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 4.06 4.83 0.160 0.190 d1 6.86 - 0.270 - a1 0.00 0.25 0.000 0.010 e 9.65 10.67 0.380 0.420 b 0.51 0.99 0.020 0.039 e1 6.22 - 0.245 - b1 0.51 0.89 0.020 0.035 e 2.54 bsc 0.100 bsc b2 1.14 1.78 0.045 0.070 h 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 l 1.78 2.79 0.070 0.110 c 0.38 0.74 0.015 0.029 l1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 l2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 l3 0.25 bsc 0.010 bsc d 8.38 9.65 0.330 0.380 l4 4.78 5.28 0.188 0.208 ecn: s-82110-rev. a, 15-sep-08 d w g: 5970
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.
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